1. Field of the Invention
The present invention relates to a pattern forming method, and a method for producing an electronic device and an electronic device, each using the same. More specifically, the invention relates to a pattern forming method, and a method for producing an electronic device and an electronic device, each using the same, each of which is suitable for a step of preparing semiconductors such as an IC, a step of preparing liquid crystals and circuit boards such as a thermal head, and further, a lithography step of other photofabrication processes. In particular, the invention relates to a pattern forming method, and a method for preparing an electronic device and an electronic device, each using the same, each of which is very suitable for exposure by an ArF exposure apparatus and an ArF liquid immersion-type projection exposure apparatus using far ultraviolet light at a wavelength of 300 nm or less as a light source.
2. Description of the Related Art
Currently, ArF liquid immersion lithography has been used in pattern formation with edges, but a resolution that can be reached by a maximum NA of water immersion lithography using a NA 1.35 lens is from 40 to 38 nm. Therefore, for the pattern formation beyond a 30 nm node, a double patterning process has been adopted (see Proc. SPIE Vol. 5992 p. 59921Q-1-16), and many processes have been proposed for the method.
As the double patterning, a spacer process has been proposed and has become a mainstream in the manufacture of an NAND flash memory (see 4th Liquid Immersion Symposium (2007) Presentation No.: PR-01, Title: Implementation of immersion lithography to NAND/CMOS lithography to NAND/CMOS device manufacturing).
Generally, in order to form a silicon oxide film on the periphery of a core material by a chemical vapor deposition (CVD) method and use this silicon oxide film as a spacer, the core material of the spacer is required to have heat resistance during CVD. Therefore, a technique in which a hard mask including a polysilicon film, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, a titanium nitride film, an amorphous carbon film, or the like is used as a core material of a spacer (see, for example, JP2006-32648A and JP2007-305970A) is a mainstream.
More specifically, in this technique, as shown in the schematic cross-sectional view of FIG. 2A, first, a substrate to be processed 13 as a second substrate, a hard mask layer 12, and a resist layer are formed in this order on a first substrate 14, and then the resist layer is subjected to exposure and development with an alkali developer to form a resist pattern 21.
Next, as shown in the schematic cross-sectional view of FIG. 2B, the hard mask layer 12 is subjected to an etching treatment using a resist pattern 21 as a mask to form a hard mask pattern 22 as a core material.
Next, as shown in the schematic cross-sectional view of FIG. 2C, a silicon oxide film 15 is formed on the substrate to be processed 13 by a chemical vapor deposition method (CVD) so as to cover the periphery of the hard mask layer 22, and as shown in the schematic cross-sectional view of FIG. 2D, an area other than the area on the side wall of the hard mask pattern 22 of the silicon oxide film 15 is removed to form a pattern including a plurality of spacers 25.
Subsequently, as shown in the schematic cross-sectional view of FIG. 2E, the hard mask pattern 22 as a core material is selectively removed, and then, as shown in the schematic cross-sectional view of FIG. 2F, the substrate to be processed 13 is subjected to an etching treatment using a pattern including a plurality of spacers 25 as a mask to form a desired pattern 24 on the first substrate 14.